In the area of distributed system co-synthesis, the target architecture can employ multiple CPUs, ASICs, and field-programmable gate arrays (FPGAs). Abstract—In this paper, we present a multiobjective hardware– software cosynthesis system, called SLOPES, for multirate low-power real-time distributed. algorithm for co-synthesis is presented that targets distributed memory Early system partitioning, along with the separate design flows for hardware and.


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They can be represented by a hierarchical architecture graph such as the one shown in FIG. PEs at intermediate nodes other than leaf nodes are known as non-terminal PEs.

Hardware-Software Co-Synthesis of Distributed Embedded Systems

The PE s at the root node forms layer 1. In this architecture model, PEs at the higher level nodes communicate with the PEs located at the distributed system co synthesis level nodes through intermediate nodes and vice versa.

However, PEs located at the same architecture layer can communicate with each other directly without going through a higher level PE if there exists a direct communication link between them. Such architectures eliminate processing and communication bottlenecks.

A non-hierarchical architecture for medium- and large-scale embedded systems can have a representation such as the one shown in FIG. For some embedded systems, such an architecture may either be very expensive or infeasible, since a Distributed system co synthesis located at the root may need to be made responsible for a variety of higher level processing functions such as user interface, communication, control, monitoring, etc.


This problem can be tackled through the concept of delegation of processing task and communication edge. To illustrate this concept, consider the task graph of FIG.


Here, a directed edge represents flow of communication, not the direction of delegation. The direction of delegation indicates the direction in which a portion of processing is moved from one PE to another to distributed system co synthesis the processing load.

Task to communicates with task t2 via edge e1. Suppose the execution time of t1 is very large, in which case it may be efficient to delegate this task to a PE at a subtending layer.

In order to facilitate this task delegation, an extra It hierarchy facilitating distributed system co synthesis HFThft1, is added to the task graph. This added task must be performed by a PE at a lower-numbered layer i.

Then t1 can be executed on a PE located at a higher-numbered layer. Similarly, as shown in FIG. In the task graph of FIG. Similarly, in order to delegate the communication of task t33 with task t35 to a higher level, HFT t34 and HFE e34 are added to the task graph.

In the case of our motivational example in FIG. During co-synthesis, if two originally consecutive tasks are allocated to the same PE, then the associated HFTs and HFEs are removed from the task graph distributed system co synthesis setting their execution and communication costs, respectively, to zero.

An Architectural Co-Synthesis Algorithm for Distributed, Embedded Computing Systems

For example, in FIG. Architectural hints are usually generated during the top-down hierarchical task graph generation process by considering the type of task, previous experience of the designer, the type of resource library, etc.

These hints are used to indicate whether: Architectural hints are not necessary for distributed system co synthesis success of the present algorithm.

However, when available, the present algorithm exploits them.


Embedded system specifications are mapped to elements of a resource library, which consists of a PE library and a link library. For each available processor, its cost, supply voltage, average quiescent power consumption, peak power constraint, memory architecture, processor-link communication characteristics, and cache characteristics are assumed to be specified.

Also, the preemption overhead is distributed system co synthesis in terms of the associated execution time, as well as the peak and average power dissipation. This overhead is determined experimentally considering the operating system overhead. It includes context switching and any other processor-specific overheads.


For each ASIC, its cost and package attributes, such as available pin count, gate count, supply voltage, and average and peak power dissipation per gate, are assumed to be specified.

Similarly, for each FPGA, its cost, supply voltage, average and peak power dissipation, initialization memory requirement, and the maximum number of programmable functional units PFUs distributed system co synthesis assumed to be specified.

The link library consists of various types of links such as point-to-point, bus, and local area network LAN.

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